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External Publications
- Mayank Agarwal; Nitin Navale; Kshitiz Malik;
Matthew I. Frank; Fetch-Criticality Reduction Through
Control Independence, International
Symposium on Computer Architecture,
(ISCA-35), June, 2008.
[pdf]
- Kshitiz Malik; Mayank Agarwal; Sam S. Stone; Kevin M. Woley;
Matthew I. Frank; Branch-mispredict Level Parallelism
(BLP) for Control Independence, International
Symposium on High-Performance Computer Architecture,
(HPCA-14), February, 2008.
[pdf]
- Kshitiz Malik; Mayank Agarwal; Vikram Dhar; Matthew I. Frank;
PaCo: Probability-based Path
Confidence Prediction, International
Symposium on High-Performance Computer Architecture,
(HPCA-14), February, 2008.
[pdf]
- Kshitiz Malik; Mayank Agarwal; Matthew I. Frank;
Adaptive Memory Synchronization (AMS):
Balancing the Risks and Benefits of Inter-thread
Load Speculation, Second Annual
Reconfigurable and Adaptive Architecture Workshop
(RAAW-2), held in conjunction with the 40th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-40),
December, 2007.
[pdf]
- Wen-Mei W. Hwu; Shane Ryoo; Sain-Zee Ueng; John H. Kelm; Issac
Gelado; Sam S. Stone; Robert E. Kidd; Sara Sadeghi Baghsorkhi;
Aqeel A. Mahesri; Stephanie Tsao; Nacho Navarro; Steve
S. Lumetta; Matthew I. Frank; Sanjay J. Patel:
Implicitly Parallel Programming Models for
Thousand-Core Microprocessors, Design
Automation Conference, (DAC-44), 2007.
[pdf]
- Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone and
Matthew I. Frank, Exploiting Postdominance for
Speculative Parallelization, Proceedings of the
International Symposium on High-Performance Computer
Architecture (HPCA-13), February, 2007.
[pdf]
- Shane Ryoo; Sain-Zee Ueng; Christopher I. Rodrigues; Robert
E. Kidd; Matthew I. Frank; Wen-mei W. Hwu: Automatic
Discovery of Coarse-Grained Parallelism in Media
Applications, Trans. High-Performance Embedded
Architectures and Compilers, 1(1):187-206, 2006.
- Sam S. Stone, Kevin M. Woley and Matthew I. Frank,
Address-Indexed Memory Disambiguation and Store-to-Load
Forwarding, Proceedings of the International
Symposium on Microarchitecture (MICRO-38), November,
2005.
[pdf]
Technical Reports
- Matthew I. Frank, System Support for Implicitly
Parallel Programming, University of Illinois Center
for Reliable and High-Performance Computing Technical Report
CRHC-07-06, October 8, 2007.
[pdf]
- Sam S. Stone, Kevin M. Woley, Kshitiz Malik, Mayank Agarwal,
Vikram Dhar and Matthew I. Frank, Synchronizing Store
Sets (SSS): Balancing the Benefits and Risks of Inter-thread
Load Speculation, University of Illinois Center for
Reliable and High-Performance Computing Technical Report
UILU-ENG-06-2221, Nov 17, 2006.
[pdf]
- Kshitiz Malik, Kevin M. Woley, Samuel S. Stone, Mayank Agarwal,
Vikram Dhar, Matthew I. Frank, Confidence Based
Out-of-Order Renaming for Speculatively Multithreaded
Processors, University of Illinois Center for Reliable
and High-Performance Computing Technical Report
UILU-ENG-06-2208, June, 9, 2006.
[pdf]
- Matthew I. Frank and Saman Amarasinghe, Scalar Queue
Conversion: Dynamic Single Assignment For Concurrent
Scheduling, University of Illinois Center for Reliable
and High-Performance Computing Technical Report
UILU-ENG-03-2215, August 2003.
[pdf]
Theses
- Sam S. Stone, Multiversioning in the Store Queue is the
Root of All Store-Forwarding Evil, M.S. Thesis,
Dept. of Electrical and Computer Engineering, University of
Illinois at Urbana Champaign, July 2007.
[pdf]
- Kevin J. Stephano, Polyflow binary rewriter :a binary
rewriter for whole program analysis and optimization,
M.S. Thesis, Dept. Electrical and Computer Engineering,
University of Illinois at Urbana-Champaign, May 2006.
- Hing Lim Chan, Memory dependence prediction using store
sets with training sets, M.S. Thesis, Dept. Electrical
and Computer Engineering, University of Illinois at
Urbana-Champaign, May 2006.
- Kshitiz Malik, Confidence Based Out-of-Order Renaming
for Dynamically Multithreaded Processors, M.S. Thesis,
Dept. Electrical and Computer Engineering, University of
Illinois at Urbana-Champaign Dec 2006.
- Mayank Agarwal, Exploiting Postdominance for
Speculative Parallelization, M.S. Thesis, Dept. of
Computer Science, University of Illinois at Urbana-Champaign
Dec 2006.
- Snehal Sanghavi, A decoupled instruction
prefetch mechanism for high throughput, M.S. Thesis,
Dept. Electrical and Computer Engineering, University of
Illinois at Urbana-Champaign, Jan 2006.
[pdf]
- Kevin M. Woley, Wakeup-set scheduling for large
instruction window processors, M.S. Thesis,
Dept. Electrical and Computer Engineering, University of
Illinois at Urbana-Champaign, Dec 2005.
[pdf]
- Todd Rafacz, Spawn Point Prediction for a PolyFlow
Processor, M.S. Thesis, Dept. Electrical and Computer
Engineering, University of Illinois at Urbana-Champaign, May
2005.
[pdf]
- Michael J. Dabrowski, The Design of a Software System
for a Small Space Satellite, M.S. Thesis,
Dept. Electrical and Computer Engineering, University of
Illinois at Urbana-Champaign, May 2005.
[pdf]
- Michael D. Tucknott, Reuse of previously fetched
instructions through the use of a reorder buffer
cache, M.S. Thesis, Dept. Electrical and Computer
Engineering, University of Illinois at Urbana-Champaign, Jan
2005.
- Benjamin J. Miller, The masked-history predictor: a
two-level branch predictor with selective global
history, M.S. Thesis, Dept. Electrical and Computer
Engineering, University of Illinois at Urbana-Champaign, Jan
2005.
- Daniel Hodges, Spill code removal via call graph
analysis, M.S. Thesis, Dept. Electrical and Computer
Engineering, University of Illinois at Urbana-Champaign, Dec
2004.
- Thomas R. Novak, Freelist-based Stack Frame
Allocation, M.S. Thesis, Dept. Electrical and Computer
Engineering, University of Illinois at Urbana-Champaign, May
2004.
[pdf]
- Wei-Ping (Thomas) Soong, LPthread: A Work-Efficient
Thread Model for Loop Parallelization, M.S. Thesis,
Dept. Electrical and Computer Engineering, University of
Illinois at Urbana-Champaign, Dec 2003.
[pdf]
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