Implicitly Parallel Architectures Group Publications

External Publications

  • Joseph L. Greathouse; Zhiqiang Ma; Matthew I. Frank; Ramesh Peri; Todd M. Austin; Demand-Driven Software Race Detection Using Hardware Performance Counters, Intl Symp Comp Arch (ISCA-38):165-176, 2011.
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  • John H. Kelm; Daniel R. Johnson; Steven S. Lumetta; Sanjay J. Patel; Matthew I. Frank; A Task-Centric Memory Model for Scalable Accelerator Architectures, IEEE Micro 30(1):29-39, 2010.
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  • John H. Kelm; Daniel R. Johnson; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel; A Task-Centric Memory Model for Scalable Accelerator Architectures, Intl Conf Parallel Arch and Compiler Techniques, (PACT-18):77-87, 2009.
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  • Nicholas Weaver; John H. Kelm; Matthew I. Frank: Emμcode: Masking Hard Faults in Complex Functional Units, Intl Conf Dependable Sys and Networks, (DSN):458-467, 2009.
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  • John H. Kelm; Daniel R. Johnson; Matthew R. Johnson; Neal Clayton Crago; William Tuohy; Aqeel Mahesri; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel; Rigel: an architecture and scalable programming interface for a 1000-core accelerator, Int'l Symp Comp Arch, (ISCA-36):140-151, 2009.
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  • Mayank Agarwal; Matthew I. Frank; SPARTAN: A Software Tool for Parallelization Bottleneck Analysis, International Workshop on Multicore Software Engineering (at ICSE), May 2009.
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  • Mayank Agarwal; Nitin Navale; Kshitiz Malik; Matthew I. Frank; Fetch-Criticality Reduction Through Control Independence, International Symposium on Computer Architecture, (ISCA-35), June, 2008.
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  • Kshitiz Malik; Mayank Agarwal; Sam S. Stone; Kevin M. Woley; Matthew I. Frank; Branch-mispredict Level Parallelism (BLP) for Control Independence, International Symposium on High-Performance Computer Architecture, (HPCA-14), February, 2008.
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  • Kshitiz Malik; Mayank Agarwal; Vikram Dhar; Matthew I. Frank; PaCo: Probability-based Path Confidence Prediction, International Symposium on High-Performance Computer Architecture, (HPCA-14), February, 2008.
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  • Kshitiz Malik; Mayank Agarwal; Matthew I. Frank; Adaptive Memory Synchronization (AMS): Balancing the Risks and Benefits of Inter-thread Load Speculation, Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2), held in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40), December, 2007.
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  • Wen-Mei W. Hwu; Shane Ryoo; Sain-Zee Ueng; John H. Kelm; Issac Gelado; Sam S. Stone; Robert E. Kidd; Sara Sadeghi Baghsorkhi; Aqeel A. Mahesri; Stephanie Tsao; Nacho Navarro; Steve S. Lumetta; Matthew I. Frank; Sanjay J. Patel: Implicitly Parallel Programming Models for Thousand-Core Microprocessors, Design Automation Conference, (DAC-44), 2007.
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  • Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone and Matthew I. Frank, Exploiting Postdominance for Speculative Parallelization, Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA-13), February, 2007.
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  • Shane Ryoo; Sain-Zee Ueng; Christopher I. Rodrigues; Robert E. Kidd; Matthew I. Frank; Wen-mei W. Hwu: Automatic Discovery of Coarse-Grained Parallelism in Media Applications, Trans. High-Performance Embedded Architectures and Compilers, 1(1):187-206, 2006.
  • Sam S. Stone, Kevin M. Woley and Matthew I. Frank, Address-Indexed Memory Disambiguation and Store-to-Load Forwarding, Proceedings of the International Symposium on Microarchitecture (MICRO-38), November, 2005.
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Technical Reports

  • Matthew I. Frank, System Support for Implicitly Parallel Programming, University of Illinois Center for Reliable and High-Performance Computing Technical Report CRHC-07-06, October 8, 2007.
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  • Sam S. Stone, Kevin M. Woley, Kshitiz Malik, Mayank Agarwal, Vikram Dhar and Matthew I. Frank, Synchronizing Store Sets (SSS): Balancing the Benefits and Risks of Inter-thread Load Speculation, University of Illinois Center for Reliable and High-Performance Computing Technical Report UILU-ENG-06-2221, Nov 17, 2006.
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  • Kshitiz Malik, Kevin M. Woley, Samuel S. Stone, Mayank Agarwal, Vikram Dhar, Matthew I. Frank, Confidence Based Out-of-Order Renaming for Speculatively Multithreaded Processors, University of Illinois Center for Reliable and High-Performance Computing Technical Report UILU-ENG-06-2208, June, 9, 2006.
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  • Matthew I. Frank and Saman Amarasinghe, Scalar Queue Conversion: Dynamic Single Assignment For Concurrent Scheduling, University of Illinois Center for Reliable and High-Performance Computing Technical Report UILU-ENG-03-2215, August 2003.
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Theses

  • Mayank Agarwal; Identifying, Quantifying, Extracting and Enhancing Implicit Parallelism, Ph.D. Thesis, Dept. of Computer Science, University of Illinois at Urbana-Champaign, 2009.
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  • Kshitiz Malik; Critical branches and lucky loads in Control-Independence architectures, Ph.D. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 2008.
  • Sam S. Stone, Multiversioning in the Store Queue is the Root of All Store-Forwarding Evil, M.S. Thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, July 2007.
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  • Kevin J. Stephano, Polyflow binary rewriter :a binary rewriter for whole program analysis and optimization, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2006.
  • Hing Lim Chan, Memory dependence prediction using store sets with training sets, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2006.
  • Kshitiz Malik, Confidence Based Out-of-Order Renaming for Dynamically Multithreaded Processors, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Dec 2006.
  • Mayank Agarwal, Exploiting Postdominance for Speculative Parallelization, M.S. Thesis, Dept. of Computer Science, University of Illinois at Urbana-Champaign Dec 2006.
  • Snehal Sanghavi, A decoupled instruction prefetch mechanism for high throughput, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Jan 2006.
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  • Kevin M. Woley, Wakeup-set scheduling for large instruction window processors, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Dec 2005.
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  • Todd Rafacz, Spawn Point Prediction for a PolyFlow Processor, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2005.
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  • Michael J. Dabrowski, The Design of a Software System for a Small Space Satellite, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2005.
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  • Michael D. Tucknott, Reuse of previously fetched instructions through the use of a reorder buffer cache, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Jan 2005.
  • Benjamin J. Miller, The masked-history predictor: a two-level branch predictor with selective global history, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Jan 2005.
  • Daniel Hodges, Spill code removal via call graph analysis, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Dec 2004.
  • Thomas R. Novak, Freelist-based Stack Frame Allocation, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2004.
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  • Wei-Ping (Thomas) Soong, LPthread: A Work-Efficient Thread Model for Loop Parallelization, M.S. Thesis, Dept. Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Dec 2003.
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